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data sheet femtoclock ? ng crystal-to-3.3v, 2.5v multiple frequency clock generator w/fanout buffer 8T49N028 8T49N028 revision 1 10/16/14 1 ?2014 integrated device technology, inc. general description the 8T49N028 is a low rms phase jitter clock synthesizer with selectable internal cryst al oscillator or external clock references and eight outputs, configurable as either lvds, lvpecl or high impedance. after power up, two frequency select pins determine one of up to four different sets of factory preprogrammed crystal or input frequency and output frequency configurations. from a single input reference, as many as three different out put frequencies may be selected for the output banks: two of these frequencies can be generated by the internal crystal oscillator, and/or external clock pre-divider, and/or a output divider, and/or b output divide r. the third output frequency is from the b output divider. device pre-programming can be overwritten through the provided i 2 c interface. examples of valid frequency config uration setups illustrate this device's flexibility, and are shown in table 3a. the specific internal register settings for each of the f our frequency sets are specified by an idt order code. custom codes can be provided by contacting idt. features ? fourth generation femtoclock ng pll technology ? eight selectable lvpecl or lvds outputs (bank selectable, two output channels per bank) ? clk, nclk input pair can accept the following differential input levels: lvpecl, lvds, hcsl ? femtoclock ng vco ra nge: 1.92ghz - 2.5ghz ? bank a and b output frequencies are mux selectable from internal crystal oscillator, reference clock input, output divider a or output divider b ? clock from output divider a, rms phase jitter at 156.25mhz (12khz - 20mhz): 225fs (typical) ? clock from output divider b, rms phase jitter at 156.25mhz (12khz - 20mhz): 219fs (typical) ? clock from output divider b, rms phase jitter at 156.25mhz (10khz - 1mhz): 165fs (typical) full 2.5v or 3.3v power supply ? full 2.5v or 3.3v power supply ? i 2 c programming interface ? pci express (2.5 gb/s), gen 2 (5 gb/s) and gen 3 (8 gb/s) jitter compliant ? -40c to 85c ambient operating temperature ? lead-free (rohs 6) packaging pin assignment 48-pin, 7mm x 7mm vfqfn package q2 nc nc v cco_a nq1 q1 nq0 q0 q3 nq2 v cco_b nq3 nq6 v cco_d v cco_c nq5 q5 nq4 q4 v ee nq7 q7 q6 v ee v ee nc xtal_in xtal_out v ee v cc fsel0 addr_sel v ee v cc fsel1 v ee v ee clk_sel clk nclk v ee lock v cca v ee nc sdata sclk nc 36 35 34 33 32 31 30 28 29 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 9 8 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37 8T49N028
revision 1 10/16/14 2 femtoclock ? ng crystal-to-3.3v, 2.5v multiple frequency clock generator w/fanout buffer 8T49N028 data sheet block diagram bank d bank c bank b bank a clk sel xtal_in xtal_out output mux select output enable 4 4 pulldown pulldown pullup pullup pulldown pulldown fsel0 fsel1 sclk sdata addr_sel clk nclk lock q2 nq2 q3 nq3 q0 nq0 q1 nq1 q4 nq4 q5 nq5 q6 nq6 q7 nq7 phase detector + charge pump ps femtoclock ng vco m[7:1] 0 1 na[5:0] 00 01 10 11 p[1:0] xtal osc pulldown pu/pd divider mux selection output type output enable selection output style 8 lvpecl or lvds 00 01 10 11 4 output divider a 8 7 output divider b 8 feedback divider pna[1:0] 2 1 0 nb[6:0] p 10mhz to 40mhz max. diff. input frequency: 600mhz ps=x2 frequency range: 5mhz to 120mhz; no limitation for ps=x1 or x0.5 phase detector frequency between 10mhz to 120mhz vco frequency between 1920mhz to 2500mhz
revision 1 10/16/14 3 femtoclock ? ng crystal-to-3.3v, 2.5v multiple frequency clock generator w/fanout buffer 8T49N028 data sheet pin description and pin characteristic tables table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. number name type description 1, 2 q0, nq0 output differential output pair. lvpecl or lvds interface levels. (bank a) 3, 4 q1, nq1 output differential output pair. lvpecl or lvds interface levels. (bank a) 5v cco_a power output supply pins for bank a 6, 7, 14, 37, 40 nc unused no connect. 8v cco_b power output supply pins for bank b 9, 10 q2, nq2 output differential output pair. lvpecl or lvds interface levels. (bank b) 11, 12 q3, nq3 output diffe rential output pair. lvpecl or lvds interface levels. (bank b) 13, 17, 21, 24, 25, 36, 41, 44, 48 v ee epad power negative supply pins. the thermal pad must be connected to v ee . 15, 16 xtal_in xtal_out input crystal oscillator interface. xtal_in is the input, xtal_out is the output. 18, 22 v cc power core supply pins. 19, 23 fsel0, fsel1 input pulldown frequency and configuration. select s between one of four factory programmable power-up default configur ations. the four configurations can have different pll states, output frequenc ies, output styles, multiplexer states and output states. these default configurations can be overwritten after power-up via i 2 c. lvcmos/lvttl interface levels. 00 = configuration 0 (default) 01 = configuration 1 10 = configuration 2 11 = configuration 3 20 addr_sel input pulldown i 2 c address select pin. lvcmos/lvttl interface levels. 26, 27 nq7, q7 output differentia l output pair. lvpecl or lvds interface levels. (bank d) 28, 29 nq6, q6 output differentia l output pair. lvpecl or lvds interface levels. (bank d) 30 v cco_d power output supply pins for bank d. 31 v cco_c power output supply pins for bank c. 32, 33 nq5, q5 output differentia l output pair. lvpecl or lvds interface levels. (bank c) 34, 35 nq4, q4 output differentia l output pair. lvpecl or lvds interface levels. (bank c) 38 sclk input pullup i 2 c clock input. lvcmos/lvttl interface levels. 39 sdata input/output pullup i 2 c data input. input: lvcmos/lvttl in terface levels. output: open drain. 42 v cca power analog supply pin. 43 lock output pll lock indicator. lvcmos/lvttl interface levels. 45 nclk input pullup / pulldown inverting differential clock input. internal resistor bias to v cc /2. 46 clk input pulldown non-inverting differential clock input. 47 clk_sel input pulldown input source control pin. lvcmos/lvttl interface levels. 0 = xtal (default) 1 = clk, nclk
revision 1 10/16/14 4 femtoclock ? ng crystal-to-3.3v, 2.5v multiple frequency clock generator w/fanout buffer 8T49N028 data sheet table 2. pin characteristics frequency configuration table 3a. frequency configuration examples note: each device supports four output frequencies (with related input or crystal value) as selected from this register settings table. note: xtal operation: using diva f out = f ref * ps * [m / (na x pna)]. using divb f out = f ref / p * ps * [m / (na x pna)]. using divb f out = f ref / p * ps * m / nb. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 3.5 pf r pulldown input pulldown resistor 51 k ? r pullup input pullup resistor 51 k ? r out output impedance lock v cco_a = v cco_b = v cco_c = v cco_d = 3.465v 22 ? v cco_a = v cco_b = v cco_c = v cco_d = 2.625v 27 ? diva frequency (mhz) divb frequency (mhz) input frequency (mhz) input clock divider p input clock prescaler ps feedback divider m output divider a pna x na output divider b nb vco frequency (mhz) 100.00 120.00 25.00 1 x2 48 24 20 2400.00 100.00 125.00 25.00 1 x2 50 25 20 2500.00 100.00 156.25 25.00 1 x2 50 25 16 2500.00 100.00 150.00 25.00 1 x2 48 24 16 2400.00 100.00 250.00 25.00 1 x2 50 25 10 2500.00 100.00 312.50 25.00 1 x2 50 25 8 2500.00 100.00 400.00 25.00 1 x2 48 24 6 2400.00 100.00 500.00 25.00 1 x2 50 25 5 2500.00 100.00 625.00 25.00 1 x2 50 25 4 2500.00 125.00 75.00 25.00 1 x1 90 18 30 2250.00 125.00 156.25 25.00 1 x2 50 20 16 2500.00 125.00 187.50 25.00 1 x1 90 18 12 2250.00 125.00 200.00 25.00 1 x2 40 16 10 2000.00 125.00 250.00 25.00 1 x2 40 16 8 2000.00 125.00 312.50 25.00 1 x2 50 20 8 2500.00 125.00 400.00 25.00 1 x2 40 16 5 2000.00 125.00 500.00 25.00 1 x2 50 20 5 2500.00 125.00 625.00 25.00 1 x2 50 20 4 2500.00 30.72 122.88 19.20 1 x2 64 80 20 2457.60 30.72 153.60 19.20 1 x2 64 80 16 2457.60 122.88 153.60 19.20 1 x2 64 20 16 2457.60 122.88 491.52 19.20 1 x2 64 20 5 2457.60 153.60 491.52 19.20 1 x2 64 16 5 2457.60 155.52 622.08 19.44 1 x2 64 16 4 2488.32 19.20 153.60 30.72 1 x2 40 128 16 2457.60 153.60 491.52 30.72 1 x2 40 16 5 2457.60
revision 1 10/16/14 5 femtoclock ? ng crystal-to-3.3v, 2.5v multiple frequency clock generator w/fanout buffer 8T49N028 data sheet table 3b. i 2 c register map note: oex, lvds_selx registers control the output bank state and not the individual output channel state. register binary register address register bit d7 d6 d5 d4 d3 d2 d1 d0 0 00000 0 m0[7] m0[6] m0[5] m0[4] m0[3] m0[2] m0[1] 1 00001 0 m1[7] m1[6] m1[5] m1[4] m1[3] m1[2] m1[1] 2 00010 0 m2[7] m2[6] m2[5] m2[4] m2[3] m2[2] m2[1] 3 00011 0 m3[7] m3[6] m3[5] m3[4] m3[3] m3[2] m3[1] 4 00100 0 nb0[6] nb0[5] nb0[4] nb0[3] nb0[2] nb0[1] nb0[0] 5 00101 0 nb1[6] nb1[5] nb1[4] nb1[3] nb1[2] nb1[1] nb1[0] 6 00110 0 nb2[6] nb2[5] nb2[4] nb2[3] nb2[2] nb2[1] nb2[0] 7 00111 0 nb3[6] nb3[5] nb3[4] nb3[3] nb3[2] nb3[1] nb3[0] 8 01000 bypass0 ps0[1] ps0[0] p0[1] p0[0] cp0[1] cp0[0] 9 01001 bypass1 ps1[1] ps1[0] p1[1] p1[0] cp1[1] cp1[0] 10 01010 bypass2 ps2[1] ps2[0] p2[1] p2[0] cp2[1] cp2[0] 11 01011 bypass3 ps3[1] ps3[0] p3[1] p3[0] cp3[1] cp3[0] 12 01100 oed0 oec0 oeb0 oea0 lv d s _ seld0 lv d s _ selc0 lv d s _ selb0 lv d s _ sela0 13 01101 oed1 oec1 oeb1 oea1 lv d s _ seld1 lv d s _ selc1 lv d s _ selb1 lv d s _ sela1 14 01110 oed2 oec2 oeb2 oea2 lv d s _ seld2 lv d s _ selc2 lv d s _ selb2 lv d s _ sela2 15 01111 oed3 oec3 oeb3 oea3 lv d s _ seld3 lv d s _ selc3 lv d s _ selb3 lv d s _ sela3 16 10000 0 0 0 0 muxb0[1] muxb0[0] muxa0[1] muxa0[0] 17 10001 0 0 0 0 muxb1[1] muxb1[0] muxa1[1] muxa1[0] 18 10010 0 0 0 0 muxb2[1] muxb2[0] muxa2[1] muxa2[0] 19 10011 0 0 0 0 muxb3[1] muxb3[0] muxa3[1] muxa3[0] 20 10100 pna0[1] pna0[0] na0[5] na0[4] na0[3] na0[2] na0[1] na0[0] 21 10101 pna1[1] pna1[0] na1[5] na1[4] na1[3] na1[2] na1[1] na1[0] 22 10110 pna2[1] pna2[0] na2[5] na2[4] na2[3] na2[2] na2[1] na2[0] 23 10111 pna3[1] pna3[0] na3[5] na3[4] na3[3] na3[2] na3[1] na3[0]
revision 1 10/16/14 6 femtoclock ? ng crystal-to-3.3v, 2.5v multiple frequency clock generator w/fanout buffer 8T49N028 data sheet table 3c. i 2 c function descriptions bits name function mn[7:1] integer feedback divider register n (n = 0...3) sets the integer feedback divider value. based on the femtoclock ng vco range, the applicable feedback dividers settings are 16 thru 250. please note the register value presents bits [7:1] of mn, the lsb of mn is not in the register. mn[7:1] bits are programmed with values to support default configuration settings for fsel[1:0]. nbn[6:0] output divider register b n (n = 0...3) sets the output divider b. the output divider value can range from 2, 3, 4, 5, 6 and 8, 10, 12 to 126 (step: 2) . see table 3i for the output divider coding. nbn[6:0] bits are programmed with values to support default configuration settings for fsel[1:0]. bypassn pll bypass register n (n = 0...3) bypasses pll output of the prescaler is routed through the output divider n to the output fanout buffer. programming a 1 to this bit bypasses the pll. programming a 0 to this bit routes the output of the prescaler through the pll. bypassn bits are programmed with values to support default configuration setting for fsel[1:0] psn(1:0) input prescaler register n (n = 0...3) sets the pll input clock prescaler value. valid prescaler values are x0.5, x1 or x2. see table 3e. set prescaler to x2 for optimum phase noise performance. psn[1:0] bits are programm ed with values to support default configuration settings for fsel[1:0]. pn[1:0] input clock divider register n (n = 0...3) sets the pll input clock divider. the divider value has the range of 1, 2, 4 and 5. see table 3e. pn[1:0] bits are programmed with values to support default configuration settings for fsel[1:0]. cpn[1:0] pll bandwidth register n (n = 0...3) sets the femtoclock ng pll bandwidth by controlling the charge pump current. see table 3j. cpn[1:0] bits are programmed with values to support default configuration settings for fsel[1:0]. oean oebn oecn oedn output enable register n (n = 0...3) sets the outputs to active or high impedance. programming a 0 to this bit sets the outputs to high impedance. programming a 1 sets the outputs to active status. oean(b ank a), oebn(bank b), oecn(bank c), oedn(bank d) bits are progra mmed with values to support default configuration settings for fsel[1:0]. lvds_selan lvds_selbn lvds_selcn lvds_seldn output style register n (n = 0...3) sets the differential output style to either lvds or lvpecl interface levels. programming a 1 to this bit sets the output styles to lvds levels. programming a 0 to this bit sets the output styles to lvpecl levels. lvds_selan(bank a), lvds_selbn(bank b), lvds_selcn (bank c), lvds_seldn(bank d) bits are programmed with values to support default configuration settings for fsel[1:0]. muxan[1:0] muxbn[1:0] mux select register n (n = 0...3) sets the multiplexer input to either crystal input, reference clock input, divider a, or divider b. see tables 3k and 3l. muxan[1:0], muxbn[1:0] bits are programmed with values to support default configuration settings for fsel[1:0]. pnan[1:0] output pre-divider register a n (n = 0...3) sets the pre output divider a. the output divider value are 2, 3, or 5. see table 3f for the output divider coding. pnan[1:0] bits are programmed with values to support default configuration settings for fsel[1:0]. nan[5:0] output divider register a n (n = 0...3) sets the output divider a. the output divider value can range from 1 to 63. see table 3g for the output divider c oding. nan[5:0] bits are programmed with values to support default configuration settings for fsel[1:0].
revision 1 10/16/14 7 femtoclock ? ng crystal-to-3.3v, 2.5v multiple frequency clock generator w/fanout buffer 8T49N028 data sheet table 3d. pll frequency range setting table 3e. feedback divider mn coding table 3f. pll pre output divider pna coding table 3g. pll output divider na coding frequency range (mhz) phase detector 10 ? 120 x2 circuitry (ps) 5 ? 120 register bit feedback divider mx mx[8:1] do not use 1 thru 15 00001000 16 00001001 18 00001010 20 00001011 22 ?? 01111100 248 01111101 250 register bit pre output divider a pna pna x [1:0] 00 2 01 3 10 5 11 2 register bit output divider n na x [5:0] 000000 n/a 000001 n/a 000010 2 000011 3 000100 4 000101 5 000110 6 000111 7 001000 8 001001 9 001010 10 001011 11 ?? 111111 63
revision 1 10/16/14 8 femtoclock ? ng crystal-to-3.3v, 2.5v multiple frequency clock generator w/fanout buffer 8T49N028 data sheet table 3h. pll output divider pna and na coding table 3i. pll output divider nb coding note: x denotes ?don?t care?. register bit register bit output divider output frequency range pna n [1:0] na n [5:0] f out_min (mhz) f out_max (mhz) 00 000000 n/a n/a n/a 00 000001 n/a n/a n/a 00 000010 4 480.00 625.00 00 ? nan * 2 (960 nan ) (1250 nan ) 00 111111 126 15.24 (approx.) 19.84 (approx.) 01 000000 n/a n/a n/a 01 000001 n/a n/a n/a 01 000010 6 320.00 416.67 01 ? nan * 3 (640 nan ) (833.33 nan ) 01 111111 189 10.16 (approx.) 13.23 (approx.) 10 000000 n/a n/a n/a 10 000001 n/a n/a n/a 10 000010 10 192.00 250.00 10 ? nan * 5 (384 n an) (500 nan ) 10 111111 315 6.10 (approx.) 7.94 (approx.) 11 000000 n/a n/a n/a 11 000001 n/a n/a n/a 11 000010 4 480.00 625.00 11 ? nan * 2 (960 nan ) (1250 nan ) 11 111111 126 15.24 (approx.) 19.84 (approx.) register bit output divider n output frequency range nb n [6:0] f out_min (mhz) f out_max (mhz) 000000x n/a n/a 0000010 2 960.00 1250.00 0000011 3 640.00 833.33 0000100 4 480.00 625.00 0000101 5 384.00 500.00 000011x 6 320.00 416.67 000100x 8 240.00 312.5 000101x 10 192.00 250.00 000110x 12 160.00 208.33 000111x 14 137.14 (approx.) 178.57 (approx.) 001000x 16 120.00 156.25 ? nb (even integer) (1920 nbn ) (2500 nbn ) 111101x 124 15.48 (approx.) 20.16 (approx.) 111111x 126 15.24 (approx.) 19.84 (approx.)
revision 1 10/16/14 9 femtoclock ? ng crystal-to-3.3v, 2.5v multiple frequency clock generator w/fanout buffer 8T49N028 data sheet table 3j. femtoclock ng pll bandwidth coding note: femtoclock ng pll stability is only guaranteed over the feedback divider ranges listed is table 3f, 3g, 3h, 3i and 3j. table 3k. muxan (n = 0...3) clock source table 3l. bank b muxn clock source register bit feedback divider value range (mhz) cpn1 cpn0 minimum maximum 0 0 16 48 0 1 48 100 10100250 11192250 register bit selected clock source muxa[1] muxa[0] 0 0 crystal input 0 1 clk, nclk 1 0 output divider a 1 1 output divider b register bit selected clock source muxb[1] muxb[0] 0 0 crystal input 01 clk, nclk 1 0 output divider a 1 1 output divider b
revision 1 10/16/14 10 femtoclock ? ng crystal-to-3.3v, 2.5v multiple frequency clock generator w/fanout buffer 8T49N028 data sheet power-up default conf iguration description the 8T49N028 supports a variety of options such as different output styles, number of programmed default frequencies, output enable and operating temperature range. the device options and default frequencies must be specified at the time of order and are programmed by idt prior to shipment. the document, programmable femtoclock ? ordering product information specifies the available order codes, including the device options and default frequency configurations. example part number: 8T49N028-001nlgi, specifies a quad frequency clock generator with default frequencies of 25 mhz, 100mhz, 156.25mhz and 156.25mhz, with four lvpecl outputs that are enabled after power-up, specified over the industrial temperature range and housed in a lead-free (6/6 rohs) vfqfn package. other order codes with respective programmed frequencies are available from idt upon request. after power-up changes to the output frequencies are controlled by fsel[1:0] or the i 2 c interface. changes to the output styles an d states of outputs (enabled or disabled) can also be controlled with the i 2 c interface after power up. table 3m. power-up default settings serial interface configuration description the 8T49N028 has an i 2 c-compatible configuration interface to access any of the internal registers (table 3b) for frequency and pll parameter programming. the 8t49n0 28 acts as a slave device on the i 2 c bus and has the address 0b110111x, where x is set by the value on the addr_sel input (see tables 3n and 3o). the interface accepts byte-oriented block write and block read operations. an address byte (p) specifies the register address (table 3b) as the byte position of the first register to writ e or read. data bytes (registers) are accessed in sequential order from the lowest to the highest byte (most significant bit first, see tables 3p, and 3q). read and write block transfers can be stopped after any complete byte transfer. it is recommended to terminate the i 2 c read or write transfer after accessing byte #23 by sending a stop command. for full electrical i 2 c compliance, it is recommended to use external pull-up resistors for sdata and sclk. the internal pull-up resistors have a size of 50k ? typical. table 3n. i 2 c device slave address addr_sel = 0 (default) table 3o. i 2 c device slave address addr_sel = 1 table 3p. block write operation table 3q. block read operation fsel1 fsel0 frequency set pll state (on or bypass) output state (active or high impedance) output style (lvds or lvpecl) 0 (default) 0 (default) frequency set 0 p ll state 0 output stat e 0 output style 0 0 1 frequency set 1 pll state 1 o utput state 1 o utput style 1 1 0 frequency set 2 pll state 2 o utput state 2 o utput style 2 1 1 frequency set 3 pll state 3 o utput state 3 o utput style 3 1101110r/w 1101111r/w bit 1 2:8 9 10 11:18 19 20:27 28 29-36 37 ... ... ... description start slave address w (0) ack address byte p ack data byte (p) ack data byte (p+1) ack data byte ... ack stop length (bits) 1711818181811 bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39-46 47 ... ... ... description start slave address w (0) a c k address byte p a c k repeated start slave address r (1) a c k data byte (p) a c k data byte (p+1) a c k data byte ... a c k stop length (bits) 1711811 7118181811
revision 1 10/16/14 11 femtoclock ? ng crystal-to-3.3v, 2.5v multiple frequency clock generator w/fanout buffer 8T49N028 data sheet absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of the product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating c onditions for extended periods may affect product reliability. note: v cco_x denotes v cco_a + v cco_b + v cco_c + v cco_d. dc electrical characteristics table 4a. power supply dc characteristics, v cc = v cco_x = 3.3v 5%, v ee = 0v, t a = -40c to 85c note: v cco_x denotes v cco_a + v cco_b + v cco_c + v cco_d. table 4b. power supply dc characteristics, v cc = v cco_x = 2.5v 5%, v ee = 0v, t a = -40c to 85c note: v cco_x denotes v cco_a + v cco_b + v cco_c + v cco_d. item rating supply voltage, v cc 3.63v inputs, v i xtal_in other input 0v to 2v -0.5v to v cc + 0.5v outputs, v o (lvcmos) outputs, i o (lvpecl) continuous current surge current outputs, i o (sdata) outputs, i o (lvds) continuous current surge current -0.5v to v cco_x + 0.5v 50ma 100ma 10ma 10ma 15ma junction temperature, t j 125c storage temperature, t stg -65 ? c to 150 ? c symbol parameter test conditio ns minimum typical maximum units v cc core supply voltage 3.135 3.3 3.465 v v cca analog supply voltage v cc ? 0.062 3.3 v cc v v cco_x output supply voltage 3.135 3.3 3.465 v i cca analog supply current 27 31 ma i ee power supply current lvpecl 250 286 ma i cc power supply current lvds 164 188 ma i cco_x output supply current lvds 140 162 ma symbol parameter test conditio ns minimum typical maximum units v cc core supply voltage 2.375 2.5 2.625 v v cca analog supply voltage v cc ? 0.054 2.5 v cc v v cco_x output supply voltage 2.375 2.5 2.625 v i cca analog supply current 23 27 ma i ee power supply current lvpecl 245 276 ma i cc power supply current lvds 160 180 ma i cco output supply current lvds 140 161 ma
revision 1 10/16/14 12 femtoclock ? ng crystal-to-3.3v, 2.5v multiple frequency clock generator w/fanout buffer 8T49N028 data sheet table 4c. lvcmos/lvttl dc characteristics, v cc = v cco_x = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c note: v cco_x denotes v cco_a + v cco_b + v cco_c + v cco_d. note 1: output terminated with 50 ? to v cco_x /2. see parameter measurement information, output load test circuit diagrams. table 4d. differential dc characteristics, v cc = v cco_x = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c note: v cco_x denotes v cco_a + v cco_b + v cco_c + v cco_d. note 1: common mode input voltage is at the cross point. table 4e. lvpecl dc characteristics, v cc = v cco_x = 3.3v5%, v ee = 0v, t a = -40c to 85c note: v cco_x denotes v cco_a + v cco_b + v cco_c + v cco_d. note 1: outputs termination with 50 ? to v cco_x ? 2v. symbol parameter test conditio ns minimum typical maximum units v ih input high voltage sclk, sdata, fsel[1:0], clk_sel, addr_sel v cc = 3.3v 2 v cc + 0.3 v v cc = 2.5v 1.7 v cc + 0.3 v v il input low voltage sclk, sdata, clk_sel, addr_sel v cc = 3.3v -0.3 0.8 v v cc = 2.5v -0.3 0.7 v fsel[1:0], v cc = 3.3v or 2.5v -0.3 0.5 v i ih input high current sclk, sdata v cc = v in = 3.465v or 2.625v 5 a fsel[1:0], clk_sel, addr_sel v cc = v in = 3.465v or 2.625v 150 a i il input low current sclk, sdata v cc = 3.465v or 2.625v, v in = 0v -150 a fsel[1:0], clk_sel, addr_sel v cc = 3.465v or 2.625v, v in = 0v -5 a v oh output high voltage; note 1 lock v cco_x = 3.465v 2.6 v v cco_x = 2.625v 1.8 v v ol output low voltage; note 1 lock v cco_x = 3.465v or 2.625v 0.7 v symbol parameter test conditio ns minimum typical maximum units i ih input high current clk, nclk v cc = v in = 3.465v or 2.625v 150 a i il input low current nclk v cc = 3.465v or 2.625v, v in = 0v -150 a clk v cc = 3.465v or 2.625v, v in = 0v -5 a v pp peak-to-peak voltage 0.2 1.3 v v cmr common mode input voltage; note 1 v ee v cc ? 1.0 v symbol parameter test conditions minimum typical maximum units v oh output high voltage; note 1 v cco_x ? 1.1 v cco_x ? 0.75 v v ol output low voltage; note 1 v cco_x ? 2.0 v cco_x ? 1.6 v v swing peak-to-peak output voltage swing 0.6 1.0 v
revision 1 10/16/14 13 femtoclock ? ng crystal-to-3.3v, 2.5v multiple frequency clock generator w/fanout buffer 8T49N028 data sheet table 4f. lvpecl dc characteristics, v cc = v cco_x = 2.5v 5%, v ee = 0v, t a = -40c to 85c note: v cco_x denotes v cco_a + v cco_b + v cco_c + v cco_d. note 1: outputs termination with 50 ? to v cc ? 2v. table 4g. lvds dc characteristics, v cc = v cco_x = 3.3v5%, v ee = 0v, t a = -40c to 85c note: v cco_x denotes v cco_a + v cco_b + v cco_c + v cco_d. table 4h. lvds dc characteristics, v cc = v cco_x = 2.5v 5%, v ee = 0v, t a = -40c to 85c note: v cco_x denotes v cco_a + v cco_b + v cco_c + v cco_d. table 5. crystal characteristics symbol parameter test conditio ns minimum typical maximum units v oh output high voltage; note 1 v cco_x ? 1.2 v cco_x ? 0.75 v v ol output low voltage; note 1 v cco_x ? 2.0 v cco_x ? 1.5 v v swing peak-to-peak output voltage swing 0.5 1.0 v symbol parameter test conditions minimum typical maximum units v od differential output voltage 247 340 454 mv ? v od v od magnitude change 50 mv v os offset voltage 1.125 1.25 1.375 v ? v os v os magnitude change 50 mv symbol parameter test conditions minimum typical maximum units v od differential output voltage 247 335 454 mv ? v od v od magnitude change 50 mv v os offset voltage 1.125 1.25 1.375 v ? v os v os magnitude change 50 mv parameter test conditions mi nimum typical maximum units mode of oscillation fundamental frequency 10 40 mhz load capacitance (c l )1218pf equivalent series resistance (esr) 50 ?
revision 1 10/16/14 14 femtoclock ? ng crystal-to-3.3v, 2.5v multiple frequency clock generator w/fanout buffer 8T49N028 data sheet ac electrical characteristics table 6a. pci express jitter specifications, v cc = v cco_x = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. fo r additional information, refer to the pci express applicat ion note section in the datasheet. note: v cco_x denotes v cco_a + v cco_b + v cco_c + v cco_d. note 1: peak-to-peak jitter after applying system transfer func tion for the common clock architecture. maximum limit for pci ex press gen 1 is 86ps peak-to-peak for a sample size of 10 6 clock periods. note 2: rms jitter after applying the two evaluation bands to the two transfer functions defined in the common clock architectu re and reporting the worst case results for each evaluation band. ma ximum limit for pci express generation 2 is 3.1ps rms for t refclk_hf_rms (high band) and 3.0ps rms for t refclk_lf_rms (low band). note 3: rms jitter after applying system transfer function for th e common clock architecture. this specification is based on th e pci express base specification revi sion 0.7, october 2009 and is subject to change pending the final release version of the specification. note 4: this parameter is guaranteed by characterization. not tested in production. symbol parameter test condit ions minimum typical maximum pcie industry specification units t j (pcie gen 1) phase jitter peak-to-peak; note 1, 4 output divider a, ? = 100mhz, 25mhz crystal input evaluation band: 0hz - nyquist (clock frequency/2) 812 86ps t refclk_hf_rms (pcie gen 2) phase jitter rms; note 2, 4 output divider a, ? = 100mhz, 25mhz crystal input high band: 1.5mhz - nyquist (clock frequency/2) 0.8 1.3 3.1 ps t refclk_lf_rms (pcie gen 2) phase jitter rms; note 2, 4 output divider a, ? = 100mhz, 25mhz crystal input low band: 10khz - 1.5mhz 0.03 0.06 3.0 ps t refclk_rms (pcie gen 3) phase jitter rms; note 3, 4 output divider a, ? = 100mhz, 25mhz crystal input evaluation band: 0hz - nyquist (clock frequency/2) 0.17 0.32 0.8 ps
revision 1 10/16/14 15 femtoclock ? ng crystal-to-3.3v, 2.5v multiple frequency clock generator w/fanout buffer 8T49N028 data sheet table 6b. ac characteristics, v cc = v cco_x = 3.3v 5% or 2.5v 5% v ee = 0v, t a = -40c to 85c symbol parameter test conditio ns minimum typical maximum units f diff_in differential input frequency; note 1 600 mhz f vco vco frequency 1920 2500 mhz t jit(?) rms phase jitter (random); note 2 25mhz crystal, f out = 25mhz, integration range: 1khz ? 1mhz 170 209 fs t jit(?) rms phase jitter (random); note 2 25mhz crystal, f out = 25mhz, integration range: 12khz ? 5mhz 321 268 fs t jit(?) rms phase jitter, random; output divider a output bank a,b note 2 25mhz crystal, f out = 100mhz, integration range: 12khz ? 20mhz 299 376 fs 25mhz crystal, f out = 125mhz, integration range: 12khz ? 20mhz 296 390 fs 25mhz crystal, f out = 156.25mhz, integration range: 12khz ? 20mhz 225 301 fs 25mhz crystal, f out = 156.25mhz, integration range: 10khz ? 1mhz 166 189 fs 25mhz crystal, f out = 250mhz, integration range: 12khz ? 20mhz 259 322 fs 30.72mhz crystal, f out = 491.52mhz, integration range: 12khz ? 20mhz 182 234 fs 19.44mhz crystal, f out = 622.08mhz, integration range: 12khz ? 20mhz 330 415 fs t jit(?) rms phase jitter, random; output divider b, output bank c,d note 2 25mhz crystal, f out = 100mhz, integration range: 12khz ? 20mhz 240 270 fs 25mhz crystal, f out = 125mhz, integration range: 12khz ? 20mhz 228 273 fs 25mhz crystal, f out = 156.25mhz, integration range: 12khz ? 20mhz 219 257 fs 25mhz crystal, f out = 156.25mhz, integration range: 10khz ? 1mhz 165 193 fs 25mhz crystal, f out = 250mhz, integration range: 12khz ? 20mhz 210 251 fs 30.72mhz crystal, f out = 491.52mhz, integration range: 12khz ? 20mhz 171 204 fs 19.44mhz crystal, f out = 622.08mhz, integration range: 12khz ? 20mhz 320 403 fs tsk(o) output skew; note 3, 4 lvpecl outputs lvds_sel = 0 130 ps lv d s outputs lvds_sel = 1 100 ps tsk(b) bank skew lvpecl outputs lvds_sel = 0 40 ps lv d s outputs lvds_sel = 1 30 ps
revision 1 10/16/14 16 femtoclock ? ng crystal-to-3.3v, 2.5v multiple frequency clock generator w/fanout buffer 8T49N028 data sheet note: v cco_x denotes v cco_a + v cco_b + v cco_c + v cco_d. note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note 1: the input frequency of the different ial input is a physical limitation of the device. follow the pll setting to insure proper functionality of the device. note 2: refer to phase noise plots. note 3: defined as skew between outputs at the same supply volt age and with equal load conditions. measured at the differential cross points. note 4: these parameters are guaranteed by characterization. not tested in production. note 5: refer to t lock and t transition in parameter measurement information. t r / t f output rise/fall time lvpecl outputs 20% - 80%, lvds_sel = 0 250 600 ps lv d s outputs 20% - 80%, lvds_sel = 1 270 500 ps odc output duty cycle output divider n ? 3; lvds_sel = 0 or 1 47 53 % output divider n = 3; lvds_sel = 0 or 1 45 55 % t lock pll lock time; note 4, 5 lock output 20 ms t transition transition time; note 4, 5 lock output 20 ms symbol parameter test conditio ns minimum typical maximum units
revision 1 10/16/14 17 femtoclock ? ng crystal-to-3.3v, 2.5v multiple frequency clock generator w/fanout buffer 8T49N028 data sheet typical phase noise at 156.25mhz noise power (dbc/hz) offset frequency (hz)
revision 1 10/16/14 18 femtoclock ? ng crystal-to-3.3v, 2.5v multiple frequency clock generator w/fanout buffer 8T49N028 data sheet parameter measureme nt information 3.3v lvpecl output load test circuit 3.3v lvds output load test circuit differential input levels 2.5v lvpecl output load test circuit 2.5v lvds output load test circuit rms phase jitter s cope qx nqx v cc, 2v -1.3v 0.165v 2v v cca v cco_x v cco_x denotes v cco_a + v cco_b + v cco_c + v cco_d 3 . 3 v 5 % v cc , v cco_x v cca v cco_x denotes v cco_a + v cco_b + v cco_c + v cco_d v cc v ee nclk clk s cope qx nqx -0.5v 0.125v v cc, 2v 2v v cca v cco_x denotes v cco_a + v cco_b + v cco_c + v cco_d v cco_x s cope qx nqx 2.5v5 % power s upply +? flo a t gnd v cc, v cco_x v cca v cco_x denotes v cco_a + v cco_b + v cco_c + v cco_d
revision 1 10/16/14 19 femtoclock ? ng crystal-to-3.3v, 2.5v multiple frequency clock generator w/fanout buffer 8T49N028 data sheet parameter measurement in formation, continued output skew lvpecl output rise/fall time offset voltage setup output duty cycle/pulse width/period lvds output rise/fall time differential output voltage setup nqx qx nqy qy nq[0:7] q[0:7] nq[0:7] q[0:7] 20% 80% 80% 20% t r t f v od nq[0:7] q[0:7]
revision 1 10/16/14 20 femtoclock ? ng crystal-to-3.3v, 2.5v multiple frequency clock generator w/fanout buffer 8T49N028 data sheet parameter measurement in formation, continued bank skew lock time & transition time t sk(b)
revision 1 10/16/14 21 femtoclock ? ng crystal-to-3.3v, 2.5v multiple frequency clock generator w/fanout buffer 8T49N028 data sheet applications information recommendations for unused input and output pins inputs: lvcmos control pins all control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. clk/nclk inputs for applications not requiring the us e of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clk to ground. crystal inputs for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from xtal_in to ground. outputs: lvpecl outputs all unused lvpecl output pairs c an be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. lvds outputs all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating, there should be no trace attached. crystal input interface the 8T49N028 has been characterized with 12pf parallel resonant crystals. the capacitor values, c1 and c2, shown in figure 1 below were determined using a 25mhz, 12pf parallel resonant crystal and were chosen to minimize the ppm error. the optimum c1 and c2 values can be slightly adjusted for different board layouts. figure 1. crystal input interface xtal_in xtal_out x1 12pf parallel crystal c1 c2 7.8pf 7.8pf
revision 1 10/16/14 22 femtoclock ? ng crystal-to-3.3v, 2.5v multiple frequency clock generator w/fanout buffer 8T49N028 data sheet overdriving the xtal interface the xtal_in input can be overdriven by an lvcmos driver or by one side of a differential driver through an ac coupling capacitor. the xtal_out pin can be left floating. the amplitude of the input signal should be between 500mv and 1.8v and the slew rate should not be less than 0.2v/ns. for 3.3v lvcmos inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. figure 2a shows an example of the interface diagram for a high speed 3.3v lvcmos driver. this c onfiguration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and changing r2 to 50 ? . the values of the resistors can be increased to reduce the loading for a slower and weaker lvcmos driver. figure 2b shows an example of the interface diagram for an lvpecl driver. this is a standard lvpecl terminati on with one side of the driver feeding the xtal_in input. it is recommended that all components in the schematics be placed in the layout. though some components might not be used, they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. figure 2a. general diagram for lvcmos driver to xtal input interface figure 2b. general diagram for lvpec l driver to xtal input interface vcc xtal_out xtal_in r1 100 r2 100 zo = 50 ohms rs ro zo = ro + rs c1 .1uf lvcmos driver xta l _ o u t xta l _ i n zo = 50 ohms c2 .1uf lvpecl driver zo = 50 ohms r1 50 r2 50 r3 50
revision 1 10/16/14 23 femtoclock ? ng crystal-to-3.3v, 2.5v multiple frequency clock generator w/fanout buffer 8T49N028 data sheet wiring the differential input to accept single-ended levels figure 3 shows how a differential input can be wired to accept single ended levels. the reference voltage v 1 = v cc /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v 1 in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v cc = 3.3v, r1 and r2 value should be adjusted to set v 1 at 1.25v. the values below are for when both the single ended swing and v cc are at the same voltage. this configuration requi res that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection bene fits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v cc + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 3. recommended schematic for wiring a diff erential input to accept single-ended levels rec eiv er + - r4 10 0 r3 10 0 rs zo = 50 ohm ro driv er vcc vcc r2 1k r1 1k c1 0.1uf ro + rs = zo v1 vc c vc c
revision 1 10/16/14 24 femtoclock ? ng crystal-to-3.3v, 2.5v multiple frequency clock generator w/fanout buffer 8T49N028 data sheet 3.3v differential clock input interface the clk /nclk accepts lvds, lvpec l, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 4a to 4d show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. figure 4a. clk/nclk input driven by a 3.3v lvpecl driver figure 4c. clk/nclk input driven by a 3.3v hcsl driver figure 4b. clk/nclk input driven by a 3.3v lvpecl driver figure 4d. clk/nclk input driven by a 3.3v lvds driver h csl *r 3 * r4 c l k n c l k 3 . 3v 3 . 3v diff e r e nti a l in p u t
revision 1 10/16/14 25 femtoclock ? ng crystal-to-3.3v, 2.5v multiple frequency clock generator w/fanout buffer 8T49N028 data sheet 2.5v differential clock input interface the clk /nclk accepts lvds, lvpec l, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 5a to 5d show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. figure 5a. clk/nclk input driven by a 2.5v lvpecl driver figure 5c. clk/nclk input driven by a 2.5v hcsl driver figure 5b. clk/nclk input driven by a 2.5v lvpecl driver figure 5d. clk/nclk input driven by a 2.5v lvds driver hcsl * r 3 33 ? ? ? ? ? ? ?
revision 1 10/16/14 26 femtoclock ? ng crystal-to-3.3v, 2.5v multiple frequency clock generator w/fanout buffer 8T49N028 data sheet lvds driver termination for a general lvds interface, the recommended value for the termination impedance (z t ) is between 90 ? and 132 ? . the actual value should be selected to match the differential impedance (z 0 ) of your transmission line. a typical point-to-point lvds design uses a 100 ? parallel resistor at the receiver and a 100 ? differential transmission-line environment. in order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. idt offers a full line of lvds compliant devices with two types of output structures: current source and voltage source. the standard termination schematic as shown in figure 6a can be used with either type of output structure. figure 6b , which can also be used with both output types, is an optional termination with center tap capacitance to help filter comm on mode noise. the capacitor value should be approximately 50pf. if using a non-standard termination, it is recommended to contact idt and confirm if the out put structure is current source or voltage source type. in addition, since these outputs are lvds compatible, the input receiver?s amplitude and common-mode input range should be verified for compatibility with the output. lv d s driver lv d s driver lv d s receiver lv d s receiver z t c z o ? z t z o ? z t z t 2 z t 2 figure 6a. standard termination figure 6b. optional termination
revision 1 10/16/14 27 femtoclock ? ng crystal-to-3.3v, 2.5v multiple frequency clock generator w/fanout buffer 8T49N028 data sheet termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. the differential outputs are lo w impedance follower outputs that generate ecl/lvpecl compatible out puts. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 7a and 7b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 7a. 3.3v lvpecl output termination figure 7b. 3.3v lvpecl output termination r1 84 ? r2 84 ? 3.3v r3 125 ? r4 125 ? z o = 50 ? z o = 50 ? input 3.3v 3.3v + _
revision 1 10/16/14 28 femtoclock ? ng crystal-to-3.3v, 2.5v multiple frequency clock generator w/fanout buffer 8T49N028 data sheet termination for 2.5v lvpecl outputs figure 8a and figure 7b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to v cco ? 2v. for v cco = 2.5v, the v cco ? 2v is very close to ground level. the r3 in figure 8b can be eliminated and the termination is shown in figure 8c. figure 8a. 2.5v lvpecl driver termination example figure 8c. 2.5v lvpecl driver termination example figure 8b. 2.5v lvpecl driver termination example 2.5v lvpecl driver v cco = 2.5v 2.5v 2.5v 50 ? 50 ? r1 250 r3 250 r2 62.5 r4 62.5 + ? 2.5v lvpecl driver v cco = 2.5v 2.5v 50 ? 50 ? r1 50 r2 50 + ? 2.5v lvpecl driver v cco = 2.5v 2.5v 50 ? 50 ? r1 50 r2 50 r3 18 + ?
revision 1 10/16/14 29 femtoclock ? ng crystal-to-3.3v, 2.5v multiple frequency clock generator w/fanout buffer 8T49N028 data sheet pci express application note pci express jitter analysis methodology models the system response to reference clock jitter. the block diagram below shows the most frequently used common clock architecture in which a copy of the reference clock is provided to both ends of the pci express link. in the jitter analysis, the transmit (tx) and receive (rx) serdes plls are modeled as well as the phase in terpolator in the receiver. these transfer functions are called h1, h2, and h3 respectively. the overall system transfer function at the receiver is: the jitter spectrum seen by the receiv er is the result of applying this system transfer function to the clock spectrum x(s) and is: in order to generate time domain jitter numbers, an inverse fourier transform is performed on x(s)*h3(s) * [h1(s) - h2(s)]. pci express common clock architecture for pci express gen 1 , one transfer function is defined and the evaluation is performed over the ent ire spectrum: dc to nyquist (e.g for a 100mhz reference clock: 0hz ? 50mhz) and the jitter result is reported in peak-peak. pcie gen 1 magnitude of transfer function for pci express gen 2 , two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. the two evaluation ranges for pci express gen 2 are 10khz ? 1.5mhz (low band) and 1.5mhz ? nyquist (high band). the plots show the individual transfer functions as well as the overall transfer function ht. pcie gen 2a magnitude of transfer function pcie gen 2b magnitude of transfer function for pci express gen 3 , one transfer function is defined and the evaluation is performed over the entire spectrum. the transfer function parameters are different from gen 1 and the jitter result is reported in rms. pcie gen 3 magnitude of transfer function for a more thorough overview of pci express jitter analysis methodology, please refer to idt application note pci express reference clock requirements. ht s ?? h3 s ?? h1 s ?? h2 s ?? ? ?? ? = ys ?? xs ?? h3 s ?? ? h1 s ?? h2 s ?? ? ?? ? =
revision 1 10/16/14 30 femtoclock ? ng crystal-to-3.3v, 2.5v multiple frequency clock generator w/fanout buffer 8T49N028 data sheet power considerations this section provides information on power dissi pation and junction temperature for the 8T49N028. equations and example calculations are also provided. lvpecl power considerations 1. power dissipation. the total power dissipation for the 8T49N028 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. the maximum currents at 85c is as follows: i ee_max = 286ma ? power (core) max = i ee_max * v cc_max = 3.465v * 286ma = 990.99mw ? power (outputs) max = 31.55mw/loaded output pair if all outputs are loaded, the total power is 8 * 31.55mw = 252.4mw total power_ max = 990.99mw + 252.4mw = 1243.39mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensu res that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 30c/w per table 7 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 1.243w * 31.55c/w = 122.3c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 7. thermal resistance ? ja for 48-lead vfqfn, forced convection ? ja vs. air flow meters per second 013 multi-layer pcb, jedec standard te st boards 30c/w 23.1c/w 19.8c/w
revision 1 10/16/14 31 femtoclock ? ng crystal-to-3.3v, 2.5v multiple frequency clock generator w/fanout buffer 8T49N028 data sheet 3. calculations and equations. the purpose of this section is to calculate the power dissipation fo r the lvpecl output pair. lvpecl output driver circuit and termination are shown in figure 9. figure 9. lvpecl driver circuit and termination to calculate power dissipation per output pair due to l oading, use the following equations which assume a 50 ? load, and a termination voltage of v cco ? 2v. ? for logic high, v out = v oh_max = v cco_max ? 0.75v (v cco_max ? v oh_max ) = 0.75v ? for logic low, v out = v ol_max = v cco_max ? 1.6v (v cco_max ? v ol_max ) = 1.6v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cco_max ? 2v))/r l ] * (v cco_max ? v oh_max ) = [(2v ? (v cco_max ? v oh_max ))/r l ] * (v cco_max ? v oh_max ) = [(2v ? 0.75v)/50 ? ] * 0.75v = 18.75mw pd_l = [(v ol_max ? (v cco_max ? 2v))/r l ] * (v cco_max ? v ol_max ) = [(2v ? (v cco_max ? v ol_max ))/r l ] * (v cco_max ? v ol_max ) = [(2v ? 1.6v)/50 ? ] * 1.6v = 12.8mw total power dissipation per output pair = pd_h + pd_l = 31.55mw v out v cco v cco - 2v q1 rl 50
revision 1 10/16/14 32 femtoclock ? ng crystal-to-3.3v, 2.5v multiple frequency clock generator w/fanout buffer 8T49N028 data sheet power considerations this section provides information on power dissi pation and junction temperature for the 8T49N028. equations and example calculations are also provided. lvds power considerations 1. power dissipation. the total power dissipation for the 8T49N028 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. the maximum currents at 85c is as follows: i cc = 188ma i cca = 31ma i ccox = 162ma ? power (core) max = (i cc_max + i cca_max + i ccox_max ) * v dd_max = (188ma + 31ma + 162ma)*3.465v = 1320.165mw total power_ max = 1320.165mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensu res that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropri ate value is 30c/w per table 7. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 1.320w * 30c/w = 124.6c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer).
revision 1 10/16/14 33 femtoclock ? ng crystal-to-3.3v, 2.5v multiple frequency clock generator w/fanout buffer 8T49N028 data sheet reliability information table 8. ? ja vs. air flow table for a 48-lead vfqfn transistor count the transistor count for 8T49N028 is 34,106. ? ja vs. air flow meters per second 013 multi-layer pcb, jedec standard te st boards 30c/w 23.1c/w 19.8c/w
revision 1 10/16/14 34 femtoclock ? ng crystal-to-3.3v, 2.5v multiple frequency clock generator w/fanout buffer 8T49N028 data sheet 48-lead vfqfn nl package ou tline and package dimensions
revision 1 10/16/14 35 femtoclock ? ng crystal-to-3.3v, 2.5v multiple frequency clock generator w/fanout buffer 8T49N028 data sheet ordering information table 8. ordering information note: for the specific -ddd order codes, refer to programmable femtoclock ? ordering product information document. part/order number marking package shipping packaging temperature 8T49N028-dddnlgi idt8T49N028-dddnlgi ? lead-free? 48-lead vfqfn tray -40 ? c to 85 ? c 8T49N028-dddnlgi8 idt8T49N028-dddnlgi ?le ad-free? 48-lead vfqfn tape & reel -40 ? c to 85 ? c
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